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| 74HC164 Description The 74HC164 is identical in pinout to the LS/ALS164. The Device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LS/ALSTTL outputs. The 74HC164 is an 8-bit, serial-it put oparallel-output shift register. Two serial data inputs, A1 and A2, are provided so that n one input May be used as a data enab le. Data is entered on each rising Edge of the clock. The activelow asynchronous Reset overrides the Clock and Serial Data inputs. Features * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V *Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices 14 1 14 1 DIP - 14 Logic Diagram SOP - 14 Package Pin Assignment Function Table Inputs RESET L H H H CLOCK X A1 X XX XH D L L Outputs QA QB... QH L... D = data input X = don' t care Q An - Q Gn = data shifted from the previous stage on a rising edge at the clock input. no change D QAn... QGn D BEIJING ESTEK ELECTRONICS CO.,LTD 1 74HC164 Absolute Maximum Ratings Symbol VCC VIN VOUT IIN mA IOUT mA ICC mA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 Unit V V V PD Tstg TL *Maximum Power Dissipation in Still Air, Plastic Storage Temperature DIP+ 750 500 -65 to +150 260 mW C C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. from 65 C 125 to C +Derating - Plastic DIP: - 10 mW/ SOIC Package: : - 7 mW/ from 65 125 C to C Recommended Operating Conditions Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must betaken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V and V IN OUT should be constrained to the range GND(VIN or V OUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). BEIJING ESTEK ELECTRONICS CO.,LTD 2 74HC164 DC Electrical Characteristics VCC Symbol Parameter Test Conditions V (Voltages Referenced to GND) Guaranteed Limit 25 C to -55 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 8.0 85 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 80 125 C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 160 A A V Unit VIH Minimum HighLevel Input Voltage Maximum Low Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH VIN= VIH or VIL Minimum HighA Level Output Voltage IOUT 20 VIN= VIH or VIL IOUT 4.0 mA IOUT 5.2 mA VIN=VIH or Maximum LowVIL Level Output Voltage IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA I 5.2 mA VIN=VCC or GND VIN=VCC or GND IOUT=0 A V VOL IIN Maximum Input Leakage Current ICC Maximum Quiescent Supply Current BEIJING ESTEK ELECTRONICS CO.,LTD 3 74HC164 AC Electrical Characteristics VCC Symbol Parameter V (C L =50pF,Input t r Guaranteed Limit 25 C to -55 C 6.0 30 35 175 35 30 205 41 35 75 15 13 10 50 10 9 5 5 5 5 5 5 80 16 14 80 16 14 1000 500 400 85 125 Unit C C =t f fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay,Clock to Q 1 and 4) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.8 24 28 220 44 37 255 51 43 95 19 16 10 65 13 11 5 5 5 5 5 5 100 20 17 100 20 17 1000 500 400 4.0 20 24 265 53 45 310 62 53 110 22 19 10 75 15 13 5 5 5 5 5 5 120 24 20 120 24 20 1000 500 400 MHz tPLH, tPHL (Figures ns ns tPHL Maximum Propagation Delay,Reset to Q (Figures 2 and 4) Maximum Output Transition Time, Any Output Maximum Input Capacitance Minimum Setup Time,A1 or A2 to Clock (Figure 3) Minimum Hold Time, Clock to A1 or A2 (Figure 3) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Reset (Figure 2) ns tTLH, tTHL CIN tSU pF ns th ns trec ns tw ns tw Minimum Pulse Width, Clock (Figure 1) ns tr, tf Maximum Input Rise and Fall Times (Figure 1) ns CPD Power Dissipation Capacitance (Per Package) Used to determine the no-load dynamic power consumption: 2 f+ICCVCC D=CPDV P Typical @25 C,VCC=5.0 V 140 pF BEIJING ESTEK ELECTRONICS CO.,LTD 4 74HC164 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit Timing Diagram BEIJING ESTEK ELECTRONICS CO.,LTD 5 74HC164 Expanded Logic Diagram Ordering Information O RDERING NU MB ER 74HC164 P ACK AGE DIP - 14 / SOP - 14 M AR KING ESTEK74HC164 Address : Postalcode:100039 Tel: 86-010-58895780 / 81 / 82 / 83 / 84 Http://www.estek.com.cn Email:sales@estek.com.cn 6A06--6A07 Rm 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing Fax : 010-58895793 REV No:01-060826 BEIJING ESTEK ELECTRONICS CO.,LTD 6 |
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